From f1664742cfa1cae3872d412b09f0c6865f553711 Mon Sep 17 00:00:00 2001
From: Junxian Huang <huangjunxian6@hisilicon.com>
Date: Sat, 22 Jun 2024 14:01:10 +0800
Subject: [PATCH 01/27] hikptool/roce: Print names of registers for
 gmv/mdb/pkt/qmm/scc/timer/trp/tsp

Print names of registers for gmv/mdb/pkt/qmm/scc/timer/trp/tsp to
improve usability.

Signed-off-by: Junxian Huang <huangjunxian6@hisilicon.com>
---
 net/roce/roce_gmv/hikp_roce_gmv.c     |  18 +++-
 net/roce/roce_mdb/hikp_roce_mdb.c     |  33 +++++-
 net/roce/roce_pkt/hikp_roce_pkt.c     |  26 ++++-
 net/roce/roce_qmm/hikp_roce_qmm.c     |  80 ++++++++++++++-
 net/roce/roce_scc/hikp_roce_scc.c     | 116 ++++++++++++++++++++-
 net/roce/roce_timer/hikp_roce_timer.c |  58 ++++++++++-
 net/roce/roce_trp/hikp_roce_trp.c     | 140 +++++++++++++++++++++++++-
 net/roce/roce_tsp/hikp_roce_tsp.c     |  84 +++++++++++++++-
 8 files changed, 541 insertions(+), 14 deletions(-)

diff --git a/net/roce/roce_gmv/hikp_roce_gmv.c b/net/roce/roce_gmv/hikp_roce_gmv.c
index 36ba665..bc01ccf 100644
--- a/net/roce/roce_gmv/hikp_roce_gmv.c
+++ b/net/roce/roce_gmv/hikp_roce_gmv.c
@@ -58,14 +58,28 @@ static int hikp_roce_gmv_idxget(struct major_cmd_ctrl *self, const char *argv)
 	return 0;
 }
 
+/* DON'T change the order of this array or add entries between! */
+static const char *g_gmv_reg_name[] = {
+	"ROCEE_VF_GMV_RO0",
+	"ROCEE_VF_GMV_RO1",
+	"ROCEE_VF_GMV_RO2",
+	"ROCEE_VF_GMV_RO3",
+	"ROCEE_VF_GMV_RO4",
+	"ROCEE_VF_GMV_RO5",
+	"ROCEE_VF_GMV_RO6",
+};
+
 static void hikp_roce_gmv_print(uint32_t reg_num, struct roce_gmv_rsp_data *gmv_rsp)
 {
+	uint8_t arr_len = HIKP_ARRAY_SIZE(g_gmv_reg_name);
 	uint32_t i;
 
 	printf("*******************GMV INFO****************\n");
-	printf("addr_offset         :              reg_data\n");
+	printf("%-40s[addr_offset] : reg_data\n", "reg_name");
 	for (i = 0; i < reg_num; i++)
-		printf("0x%08X : 0x%08X\n", gmv_rsp->reg_offset[i], gmv_rsp->reg_data[i]);
+		printf("%-40s[0x%08X] : 0x%08X\n",
+		       i < arr_len ? g_gmv_reg_name[i] : "",
+		       gmv_rsp->reg_offset[i], gmv_rsp->reg_data[i]);
 	printf("*******************************************\n");
 }
 
diff --git a/net/roce/roce_mdb/hikp_roce_mdb.c b/net/roce/roce_mdb/hikp_roce_mdb.c
index 374f100..b2b2c41 100644
--- a/net/roce/roce_mdb/hikp_roce_mdb.c
+++ b/net/roce/roce_mdb/hikp_roce_mdb.c
@@ -48,14 +48,43 @@ static int hikp_roce_mdb_clear_set(struct major_cmd_ctrl *self, const char *argv
 	return 0;
 }
 
+/* DON'T change the order of this array or add entries between! */
+static const char *g_mdb_reg_name[] = {
+	"ROCEE_DWQE_WQE_ISSUE_CNT",
+	"ROCEE_DWQE_WQE_EXEC_CNT",
+	"ROCEE_DWQE_WQE_DROP_CNT",
+	"ROCEE_DWQE_SQDB_ISSUE_CNT",
+	"ROCEE_DWQE_SQDB_EXEC_CNT",
+	"ROCEE_MBX_ISSUE_CNT",
+	"ROCEE_MBX_EXEC_CNT",
+	"ROCEE_DB_ISSUE_CNT",
+	"ROCEE_DB_EXEC_CNT",
+	"ROCEE_EQDB_ISSUE_CNT",
+	"MDB_ALM",
+	"ROCEE_MDB_EMPTY",
+	"ROCEE_MDB_FULL",
+	"MDB_STA_0",
+	"MDB_STA_1",
+	"MDB_STA_2",
+	"MDB_MEM_INIT_DONE",
+	"ROCEE_MDB_ECC_ERR",
+	"ROCEE_MDB_ECC_ERR_INFO",
+	"MDB_STA_3",
+	"MDB_STA_4",
+	"MDB_STA_5",
+};
+
 static void hikp_roce_mdb_print(uint32_t reg_num, struct roce_mdb_rsp_data *mdb_rsp)
 {
+	uint8_t arr_len = HIKP_ARRAY_SIZE(g_mdb_reg_name);
 	uint32_t i;
 
 	printf("**************MDB INFO*************\n");
-	printf("addr_offset      :         reg_data\n");
+	printf("%-40s[addr_offset] : reg_data\n", "reg_name");
 	for (i = 0; i < reg_num; i++)
-		printf("0x%08X : 0x%08X\n", mdb_rsp->reg_offset[i], mdb_rsp->reg_data[i]);
+		printf("%-40s[0x%08X] : 0x%08X\n",
+		       i < arr_len ? g_mdb_reg_name[i] : "",
+		       mdb_rsp->reg_offset[i], mdb_rsp->reg_data[i]);
 	printf("***********************************\n");
 }
 
diff --git a/net/roce/roce_pkt/hikp_roce_pkt.c b/net/roce/roce_pkt/hikp_roce_pkt.c
index e710e08..74294c6 100644
--- a/net/roce/roce_pkt/hikp_roce_pkt.c
+++ b/net/roce/roce_pkt/hikp_roce_pkt.c
@@ -62,14 +62,38 @@ static int hikp_roce_pkt_get_data(struct hikp_cmd_ret **cmd_ret, struct roce_pkt
 	return ret;
 }
 
+/* DON'T change the order of this array or add entries between! */
+static const char *g_pkt_reg_name[] = {
+	"ROCEE_RC_PKT_RX_CNT",
+	"ROCEE_UD_PKT_RX_CNT",
+	"ROCEE_XRC_PKT_RX_CNT",
+	"ROCEE_PKT_RX_CNT",
+	"ROCEE_ERR_PKT_RX_CNT",
+	"ROCEE_CNP_PKT_RX_CNT",
+	"TRP_RX_ERR_FLAG",
+	"RX_BUFF_CNT",
+	"ROCEE_RC_PKT_TX_CNT",
+	"ROCEE_UD_PKT_TX_CNT",
+	"ROCEE_XRC_PKT_TX_CNT",
+	"ROCEE_PKT_TX_CNT",
+	"ROCEE_ERR_PKT_TX_CNT",
+	"ROCEE_CNP_PKT_TX_CNT",
+	"TRP_GET_MPT_ERR_PKT_CNT",
+	"TRP_GET_IRRL_ERR_PKT_CNT",
+};
+
 static void hikp_roce_pkt_print(uint32_t total_block_num,
 				const uint32_t *offset, const uint32_t *data)
 {
+	uint8_t arr_len = HIKP_ARRAY_SIZE(g_pkt_reg_name);
 	uint32_t i;
 
 	printf("**************PKT INFO*************\n");
+	printf("%-40s[addr_offset] : reg_data\n", "reg_name");
 	for (i = 0; i < total_block_num; i++)
-		printf("[0x%08X] : 0x%08X\n", offset[i], data[i]);
+		printf("%-40s[0x%08X] : 0x%08X\n",
+		       i < arr_len ? g_pkt_reg_name[i] : "",
+		       offset[i], data[i]);
 	printf("***********************************\n");
 }
 
diff --git a/net/roce/roce_qmm/hikp_roce_qmm.c b/net/roce/roce_qmm/hikp_roce_qmm.c
index e440b82..fa4e18a 100644
--- a/net/roce/roce_qmm/hikp_roce_qmm.c
+++ b/net/roce/roce_qmm/hikp_roce_qmm.c
@@ -58,14 +58,90 @@ static int hikp_roce_qmm_bank_get(struct major_cmd_ctrl *self, const char *argv)
 	return 0;
 }
 
+/* DON'T change the order of these arrays or add entries between! */
+static const char *g_qmm_top_reg_name[] = {
+	"ROCEE_QMM_SRQC_ALM",
+	"ROCEE_QMM_MPT_ALM",
+	"ROCEE_QMM_ECC_ERR",
+	"QMM_AXI_RESP_ERR",
+	"ROCEE_LPRC_RO",
+	"ROCEE_LPRC_RC",
+	"QMM_LPRC_EMPTY_RD",
+	"QPC_DMAE_EMPTY_RD",
+	"QMM_LPRC_FULL_WR",
+	"QPC_DMAE_FULL_WR",
+	"ROCEE_QMM_QPC_ALM",
+	"ROCEE_QMM_GMV_ALM",
+};
+
+static const char *g_qmm_cqc_reg_name[] = {
+	"ROCEE_CQC_SRH_REQ_RO_BK0",
+	"ROCEE_CQC_SRH_REQ_RO_BK1",
+	"ROCEE_CQC_ECC_ERR",
+	"ROCEE_CQC_RESP_ERR",
+	"CQC_RW_REQ_RO_BK0",
+	"CQC_RW_REQ_RO_BK1",
+	"ROCEE_QMM_CQC_ALM",
+};
+
+static const char *g_qmm_qpc_reg_name[] = {
+	"QMM_QPC_SRH_CNT_0",
+	"QMM_QPC_SRH_CNT_1",
+	"ROCEE_QPC_EMPTY_RD",
+	"ROCEE_QPC_FULL_WR",
+	"ROCEE_QPC_SRH_REQ_RO_0",
+	"ROCEE_QPC_SRH_REQ_RO_1",
+	"QMM_QPC_CLR_CNT0_0",
+	"QMM_QPC_CLR_CNT1_0",
+	"QMM_QPC_CLR_CNT2_0",
+	"QMM_QPC_CLR_CNT3_0",
+	"QMM_QPC_CLR_CNT0_1",
+	"QMM_QPC_CLR_CNT1_1",
+	"QMM_QPC_CLR_CNT2_1",
+	"QMM_QPC_CLR_CNT3_1",
+	"QPC_RW_REQ_RO_0",
+	"QPC_RW_REQ_RO_1",
+	"QPC_WQE_ECC_ERR",
+};
+
+static const struct reg_name_info {
+	enum roce_qmm_cmd_type sub_cmd;
+	const char **reg_name;
+	uint8_t arr_len;
+} g_qmm_reg_name_info_table[] = {
+	{QMM_SHOW_CQC, g_qmm_cqc_reg_name, HIKP_ARRAY_SIZE(g_qmm_cqc_reg_name)},
+	{QMM_SHOW_QPC, g_qmm_qpc_reg_name, HIKP_ARRAY_SIZE(g_qmm_qpc_reg_name)},
+	{QMM_SHOW_TOP, g_qmm_top_reg_name, HIKP_ARRAY_SIZE(g_qmm_top_reg_name)},
+};
+
 static void hikp_roce_qmm_print(struct roce_qmm_rsp_data *qmm_rsp)
 {
+	const char **reg_name;
+	uint8_t arr_len;
 	int index = 0;
 
+	for (index = 0; index < HIKP_ARRAY_SIZE(g_qmm_reg_name_info_table); index++) {
+		if (g_qmm_reg_name_info_table[index].sub_cmd != g_roce_qmm_param.sub_cmd)
+			continue;
+		arr_len = g_qmm_reg_name_info_table[index].arr_len;
+		reg_name = g_qmm_reg_name_info_table[index].reg_name;
+		break;
+	}
+
+	if (index == HIKP_ARRAY_SIZE(g_qmm_reg_name_info_table)) {
+		printf("can't find reg name table for roce_qmm sub_cmd %u.\n",
+		       g_roce_qmm_param.sub_cmd);
+		return;
+	}
+
 	printf("**************QMM %s INFO*************\n",
 	       g_roce_qmm_param.sub_name);
+	printf("%-40s[addr_offset] : reg_data\n", "reg_name");
+	index = 0;
 	while (index < qmm_rsp->reg_num) {
-		printf("0x%08X : 0x%08X\n", qmm_rsp->qmm_content[index][0],
+		printf("%-40s[0x%08X] : 0x%08X\n",
+		       index < arr_len ? reg_name[index] : "",
+		       qmm_rsp->qmm_content[index][0],
 		       qmm_rsp->qmm_content[index][1]);
 		index++;
 	}
@@ -125,7 +201,7 @@ exec_error:
 
 static void hikp_roce_qmm_execute(struct major_cmd_ctrl *self)
 {
-	const struct cmd_type_info {
+	static const struct cmd_type_info {
 		enum roce_qmm_cmd_type sub_cmd;
 		enum roce_qmm_cmd_type sub_ext_cmd;
 		const char *sub_name;
diff --git a/net/roce/roce_scc/hikp_roce_scc.c b/net/roce/roce_scc/hikp_roce_scc.c
index fe08873..76c0ca6 100644
--- a/net/roce/roce_scc/hikp_roce_scc.c
+++ b/net/roce/roce_scc/hikp_roce_scc.c
@@ -208,14 +208,128 @@ static int hikp_roce_scc_get_next_data(struct roce_scc_head *res_head,
 	return 0;
 }
 
+/* DON'T change the order of these arrays or add entries between! */
+static const char *g_scc_common_reg_name[] = {
+	"SCC_MODE_SEL",
+	"SCC_OUTSTANDING_CTRL",
+	"SCC_FW_BASE_ADDR",
+	"SCC_MEM_START_INIT",
+	"SCC_MEM_INIT_DONE",
+	"SCC_FW_REQ_CNT",
+	"SCC_FW_RSP_CNT",
+	"SCC_FW_CNT_CTRL",
+	"SCC_GLB_OUTSTANDING",
+	"SCC_AXI_OUTSTANDING",
+	"SCC_FW_REQRSP_CNT0",
+	"SCC_FW_REQRSP_CNT1",
+	"SCC_OUTSTANDING_ID",
+	"SCC_OUTSTANDING_STS",
+	"SCC_CACHEMISS_LOAD_CNT",
+	"SCC_CACHEMISS_STORE_CNT",
+	"FW_PROCESS_TIME",
+	"SCC_INT_EN",
+	"SCC_INT_SRC",
+	"SCC_ECC_1BIT_CNT",
+	"SCC_ECC_1BIT_INFO",
+	"SCC_ECC_MBIT_INFO",
+	"ECC_ERR_INJ_SEL",
+	"CTX_RDWR_ERR_INFO",
+	"SCC_FW_REQRSP_CNT2",
+	"SCC_LOAD_CAL_CFG_0",
+	"SCC_LOAD_CAL_CFG_1",
+	"SCC_LOAD_CAL_CFG_2",
+	"SCC_LOAD_CAL_CFG_3",
+	"SCC_LOAD_CAL_CFG_4",
+	"SCC_LOAD_CAL_CFG_5",
+	"SCC_LOAD_CAL_CFG_6",
+	"SCC_LOAD_CAL_CFG_7",
+	"SCC_MAX_PROCESS_TIME",
+	"SCC_TIMEOUT_SET",
+	"SCC_TIMEOUT_CNT",
+	"SCC_TIME_STA_EN",
+	"SCC_INPUT_REQ_CNT",
+	"SCC_OUTPUT_RSP_CNT",
+	"SCC_INOUT_CNT_CFG",
+};
+
+static const char *g_scc_dcqcn_reg_name[] = {
+	"SCC_TEMP_CFG0",
+	"SCC_TEMP_CFG1",
+	"SCC_TEMP_CFG2",
+	"SCC_TEMP_CFG3",
+	"ROCEE_CNP_PKT_RX_CNT",
+	"ROCEE_CNP_PKT_TX_CNT",
+	"ROCEE_ECN_DB_CNT0",
+	"ROCEE_ECN_DB_CNT1",
+	"ROCEE_ECN_DB_CNT2",
+	"ROCEE_ECN_DB_CNT3",
+};
+
+static const char *g_scc_dip_reg_name[] = {
+	"SCC_TEMP_CFG0",
+	"SCC_TEMP_CFG1",
+	"SCC_TEMP_CFG2",
+	"SCC_TEMP_CFG3",
+};
+
+static const char *g_scc_hc3_reg_name[] = {
+	"SCC_TEMP_CFG0",
+	"SCC_TEMP_CFG1",
+	"SCC_TEMP_CFG2",
+	"SCC_TEMP_CFG3",
+};
+
+static const char *g_scc_ldcp_reg_name[] = {
+	"SCC_TEMP_CFG0",
+	"SCC_TEMP_CFG1",
+	"SCC_TEMP_CFG2",
+	"SCC_TEMP_CFG3",
+};
+
+static const char *g_scc_cfg_reg_name[] = {
+	"ROCEE_TM_CFG",
+};
+
+static const struct reg_name_info {
+	enum roce_scc_type sub_cmd;
+	const char **reg_name;
+	uint8_t arr_len;
+} g_scc_reg_name_info_table[] = {
+	{COMMON, g_scc_common_reg_name, HIKP_ARRAY_SIZE(g_scc_common_reg_name)},
+	{DCQCN, g_scc_dcqcn_reg_name, HIKP_ARRAY_SIZE(g_scc_dcqcn_reg_name)},
+	{DIP, g_scc_dip_reg_name, HIKP_ARRAY_SIZE(g_scc_dip_reg_name)},
+	{HC3, g_scc_hc3_reg_name, HIKP_ARRAY_SIZE(g_scc_hc3_reg_name)},
+	{LDCP, g_scc_ldcp_reg_name, HIKP_ARRAY_SIZE(g_scc_ldcp_reg_name)},
+	{CFG, g_scc_cfg_reg_name, HIKP_ARRAY_SIZE(g_scc_cfg_reg_name)},
+};
+
 static void hikp_roce_scc_print(uint8_t total_block_num,
 				const uint32_t *offset, const uint32_t *data)
 {
+	const char **reg_name;
+	uint8_t arr_len;
 	uint32_t i;
 
+	for (i = 0; i < HIKP_ARRAY_SIZE(g_scc_reg_name_info_table); i++) {
+		if (g_scc_reg_name_info_table[i].sub_cmd != g_roce_scc_param_t.sub_cmd)
+			continue;
+		arr_len = g_scc_reg_name_info_table[i].arr_len;
+		reg_name = g_scc_reg_name_info_table[i].reg_name;
+		break;
+	}
+
+	if (i == HIKP_ARRAY_SIZE(g_scc_reg_name_info_table)) {
+		printf("can't find reg name table for roce_scc sub_cmd %u.\n",
+		       g_roce_scc_param_t.sub_cmd);
+		return;
+	}
+
 	printf("**************SCC INFO*************\n");
+	printf("%-40s[addr_offset] : reg_data\n", "reg_name");
 	for (i = 0; i < total_block_num; i++)
-		printf("[0x%08X] : 0x%08X\n", offset[i], data[i]);
+		printf("%-40s[0x%08X] : 0x%08X\n",
+		       i < arr_len ? reg_name[i] : "",
+		       offset[i], data[i]);
 	printf("***********************************\n");
 }
 
diff --git a/net/roce/roce_timer/hikp_roce_timer.c b/net/roce/roce_timer/hikp_roce_timer.c
index 05ad3e1..a36257e 100644
--- a/net/roce/roce_timer/hikp_roce_timer.c
+++ b/net/roce/roce_timer/hikp_roce_timer.c
@@ -44,12 +44,62 @@ static int hikp_roce_timer_clear_set(struct major_cmd_ctrl *self, const char *ar
 	return 0;
 }
 
-static void hikp_roce_timer_print(struct roce_timer_rsp_data *timer_rsp)
+/* DON'T change the order of these arrays or add entries between! */
+static const char *g_timer_qpc_reg_name[] = {
+	"QPC_AXI_ERR",
+	"QPC_SEARCH_CNT",
+	"QPC_DB_SEND_CNT",
+	"FIFO_FILL0",
+	"FIFO_FILL1",
+	"FIFO_FILL2",
+	"FIFO_OVER_FLOW",
+	"QPC_START_CNT",
+	"QPC_DB_SEND_NUM_CNT",
+	"ROCEE_TIMER_QPC_ECC_ERR",
+	"ROCEE_TIMER_QPC_ECC_ERR_INFO",
+	"START_TYPE_ERR_CNT",
+};
+
+static const char *g_timer_cqc_reg_name[] = {
+	"TIMER_MEM_INIT_DONE",
+	"CQC_AXI_ERR",
+	"CQC_SEARCH_CNT",
+	"CQC_DB_SEND_CNT",
+	"CQC_FIFO_FILL0",
+	"CQC_FIFO_FILL1",
+	"CQC_FIFO_FILL2",
+	"CQC_START_CNT",
+	"CQC_DB_SEND_NUM_CNT",
+	"FLR_DONE_STATE",
+	"ZERO_ADDR_ACC",
+	"ROCEE_TIMER_CQC_ECC_ERR",
+	"ROCEE_TIMER_CQC_ECC_ERR_INFO",
+	"TIMER_STA_0",
+	"CQC_LOSE_DB_CNT",
+	"TIMER_TDP_DONE_CNT",
+	"CQC_PAGE_OVER_CNT",
+};
+
+static void hikp_roce_timer_print(struct roce_timer_rsp_data *timer_rsp,
+				  enum roce_timer_cmd_type cmd_type)
 {
+	const char **reg_name;
+	uint8_t arr_len;
 	int index = 0;
 
+	if (cmd_type == TIMER_SHOW_QPC) {
+		reg_name = g_timer_qpc_reg_name;
+		arr_len = HIKP_ARRAY_SIZE(g_timer_qpc_reg_name);
+	} else {
+		reg_name = g_timer_cqc_reg_name;
+		arr_len = HIKP_ARRAY_SIZE(g_timer_cqc_reg_name);
+	}
+
+	printf("%-40s[addr_offset] : reg_data\n", "reg_name");
 	while (index < timer_rsp->reg_num) {
-		printf("0x%08X : 0x%08X\n", timer_rsp->timer_content[index][0],
+		printf("%-40s[0x%08X] : 0x%08X\n",
+		       index < arr_len ? reg_name[index] : "",
+		       timer_rsp->timer_content[index][0],
 		       timer_rsp->timer_content[index][1]);
 		index++;
 	}
@@ -83,7 +133,7 @@ static int hikp_roce_timer_show_qpc(struct major_cmd_ctrl *self)
 	}
 
 	printf("**************QPC TIMER INFO*************\n");
-	hikp_roce_timer_print(timer_rsp);
+	hikp_roce_timer_print(timer_rsp, TIMER_SHOW_QPC);
 out:
 	free(cmd_ret);
 	cmd_ret = NULL;
@@ -117,7 +167,7 @@ static int hikp_roce_timer_show_cqc(struct major_cmd_ctrl *self)
 	}
 
 	printf("**************CQC TIMER INFO*************\n");
-	hikp_roce_timer_print(timer_rsp);
+	hikp_roce_timer_print(timer_rsp, TIMER_SHOW_CQC);
 out:
 	free(cmd_ret);
 	cmd_ret = NULL;
diff --git a/net/roce/roce_trp/hikp_roce_trp.c b/net/roce/roce_trp/hikp_roce_trp.c
index fad3317..61f0511 100644
--- a/net/roce/roce_trp/hikp_roce_trp.c
+++ b/net/roce/roce_trp/hikp_roce_trp.c
@@ -231,14 +231,152 @@ static int hikp_roce_trp_get_next_data(struct roce_trp_head *res_head,
 	return 0;
 }
 
+/* DON'T change the order of these arrays or add entries between! */
+static const char *g_trp_common_reg_name[] = {
+	"GEN_AC_QP_FIFO_FULL",
+	"GEN_AC_QP_FIFO_EMPTY",
+	"GEN_AC_QP_INNER_STA_0",
+	"GEN_AC_QP_INNER_STA_1",
+	"GEN_AC_QP_ALM",
+	"GEN_AC_QP_TSP_CQE_CNT",
+	"TRP_GET_PBL_FULL",
+	"TRP_GET_PBL_EMPTY",
+	"TRP_GET_PBL_INNER_ALM",
+	"TRP_GET_PBL_INNER_STA",
+	"TRP_GET_MPT_FSM",
+	"TRP_GET_MPT_EMPTY",
+	"TRP_GET_MPT_INNER_ALM",
+	"TRP_GET_MPT_INNER_STA",
+	"TRP_GET_SGE_FSM",
+	"TRP_GET_SGE_EMPTY",
+	"TRP_GET_SGE_INNER_ALM",
+	"TRP_GET_SGE_INNER_STA",
+	"TRP_GET_BA_EMPTY",
+	"TRP_GET_BA_INNER_ALM",
+	"TRP_GET_BA_INNER_STA",
+	"TRP_DMAECMD_EMPTY_0",
+	"TRP_DMAECMD_EMPTY_1",
+	"TRP_DMAECMD_FULL",
+	"TRP_GET_IRRL_FSM",
+	"TRP_GET_IRRL_FULL",
+	"TRP_GET_IRRL_EMPTY",
+	"TRP_GET_IRRL_INNER_ALM",
+	"TRP_GET_IRRL_INNER_STA",
+	"TRP_GET_QPC_FSM",
+	"TRP_GET_QPC_INNER_ALM",
+	"TRP_GET_QPC_INNER_STA",
+	"ROCEE_TRP_ECC_ERR_INFO",
+	"ROCEE_TRP_ECC1B",
+	"ROCEE_TRP_ECC2B",
+	"ROCEE_TRP_FUN_RST_DFX",
+	"TRP_GET_MPT_ERR_FLG",
+	"TRP_GET_IRRL_ERR_FLG",
+	"TRP_GET_QPC_ERR_FLG",
+	"ROCEE_ECN_DB_CNT",
+	"GEN_AC_QP_TSP_AE_CNT",
+	"GEN_AC_QP_MDB_CQE_CNT",
+	"GEN_AC_QP_LPRC_CQE_CNT",
+	"TRP_CNP_CNT",
+	"TRP_SGE_ERR_DROP_LEN",
+	"TRP_SGE_AXI_CNT",
+};
+
+static const char *g_trp_trp_rx_reg_name[] = {
+	"TRP_RX_CHECK_EN",
+	"TRP_RX_WR_PAYL_AXI_ERR",
+	"ROCEE_TRP_RX_STA",
+	"RX_FIFO_FULL",
+	"RX_FIFO_EMPTY_0",
+	"RX_FIFO_EMPTY_1",
+	"HEAD_BUFF_ECC",
+	"HEAD_BUFF_ECC_ADDR",
+	"TRP_RX_FIFO_EMPTY_0",
+	"TRP_RX_FIFO_EMPTY_1",
+	"TRP_RX_FIFO_EMPTY_2",
+	"TRP_RX_FIFO_EMPTY_3",
+};
+
+static const char *g_trp_gen_ac_reg_name[] = {
+	"GEN_AC_CQ_FIFO_FULL",
+	"GEN_AC_CQ_FIFO_EMPTY",
+	"GEN_AC_CQ_INNER_STA",
+	"GEN_AC_CQ_ALM",
+	"GEN_AC_CQ_CQE_CNT_0",
+	"GEN_AC_CQ_CQE_CNT_1",
+	"GEN_AC_CQ_CQE_CNT_2",
+	"GEN_AC_CQ_CQE_CNT_3",
+	"ROCEE_GENAC_ECC_ERR_INFO",
+	"ROCEE_GENAC_ECC1B",
+	"ROCEE_GENAC_ECC2B",
+	"GEN_AC_DMAECMD_STA",
+	"GEN_AC_DMAECMD_ALM",
+	"SWQE_LINK_STA",
+	"SWQE_LINK_ALM",
+	"GEN_AC_CQ_MAIN_STA_0",
+	"GEN_AC_CQ_MAIN_ALM",
+	"GEN_AC_CQ_MAIN_STA_1",
+	"POE_DFX_0",
+	"POE_DFX_1",
+	"POE_DFX_2",
+};
+
+static const char *g_trp_payl_reg_name[] = {
+	"ROCEE_EXT_ATOMIC_DFX_0",
+	"ROCEE_EXT_ATOMIC_DFX_1",
+	"ROCEE_EXT_ATOMIC_DFX_2",
+	"ROCEE_EXT_ATOMIC_DFX_3",
+	"ATOMIC_DFX_0",
+	"ATOMIC_DFX_1",
+	"ATOMIC_DFX_2",
+	"WR_PAYL_DFX_1",
+	"PAYL_BUFF_DFX_0",
+	"PAYL_BUFF_DFX_1",
+	"PAYL_BUFF_DFX_2",
+	"PAYL_BUFF_DFX_3",
+	"PAYL_BUFF_DFX_4",
+	"WR_PAYL_DFX_RC",
+	"WR_PAYL_DFX_RO",
+	"WR_PAYL_1_OST_NUM",
+};
+
+static const struct reg_name_info {
+	enum roce_trp_type sub_cmd;
+	const char **reg_name;
+	uint8_t arr_len;
+} g_trp_reg_name_info_table[] = {
+	{COMMON, g_trp_common_reg_name, HIKP_ARRAY_SIZE(g_trp_common_reg_name)},
+	{TRP_RX, g_trp_trp_rx_reg_name, HIKP_ARRAY_SIZE(g_trp_trp_rx_reg_name)},
+	{GEN_AC, g_trp_gen_ac_reg_name, HIKP_ARRAY_SIZE(g_trp_gen_ac_reg_name)},
+	{PAYL, g_trp_payl_reg_name, HIKP_ARRAY_SIZE(g_trp_payl_reg_name)},
+};
+
 static void hikp_roce_trp_print(uint8_t total_block_num,
 				const uint32_t *offset, const uint32_t *data)
 {
+	const char **reg_name;
+	uint8_t arr_len;
 	uint32_t i;
 
+	for (i = 0; i < HIKP_ARRAY_SIZE(g_trp_reg_name_info_table); i++) {
+		if (g_trp_reg_name_info_table[i].sub_cmd != g_roce_trp_param_t.sub_cmd)
+			continue;
+		arr_len = g_trp_reg_name_info_table[i].arr_len;
+		reg_name = g_trp_reg_name_info_table[i].reg_name;
+		break;
+	}
+
+	if (i == HIKP_ARRAY_SIZE(g_trp_reg_name_info_table)) {
+		printf("can't find reg name table for roce_trp sub_cmd %u.\n",
+		       g_roce_trp_param_t.sub_cmd);
+		return;
+	}
+
 	printf("**************TRP INFO*************\n");
+	printf("%-40s[addr_offset] : reg_data\n", "reg_name");
 	for (i = 0; i < total_block_num; i++)
-		printf("[0x%08X] : 0x%08X\n", offset[i], data[i]);
+		printf("%-40s[0x%08X] : 0x%08X\n",
+		       i < arr_len ? reg_name[i] : "",
+		       offset[i], data[i]);
 	printf("***********************************\n");
 }
 
diff --git a/net/roce/roce_tsp/hikp_roce_tsp.c b/net/roce/roce_tsp/hikp_roce_tsp.c
index 5bb2649..b16f0a4 100644
--- a/net/roce/roce_tsp/hikp_roce_tsp.c
+++ b/net/roce/roce_tsp/hikp_roce_tsp.c
@@ -137,14 +137,96 @@ static int hikp_roce_tsp_get_data(struct hikp_cmd_ret **cmd_ret,
 	return ret;
 }
 
+/* DON'T change the order of these arrays or add entries between! */
+static const char *g_tsp_common_reg_name[] = {
+	"ROCEE_TPP_ECC_ERR",
+	"ROCEE_TWP_STA",
+	"ROCEE_TWP_ALM",
+	"ROCEE_TWP_STA1",
+	"TSP_INDRECT_RW_STA",
+	"TSP_INDRECT_RD_CTRL",
+	"TSP_INDRECT_RD_DATA",
+	"ROCEE_TSP_OVF",
+};
+
+static const char *g_tsp_tdp_reg_name[] = {
+	"TDP_M_MEM_INIT_DONE",
+	"TDP_M_ECC1B",
+	"TDP_M_ECC2B",
+	"TDP_M_ECC_ERR_INFO",
+	"TDP_M_ALM",
+	"ROCEE_TDP_CNT_CFG0",
+	"ROCEE_TDP_CNT_CFG1",
+	"ROCEE_TDP_IN_CNT_ENB",
+	"ROCEE_TDP_TWP_CNT0_CFG",
+	"ROCEE_TDP_TWP_CNT1_CFG",
+	"ROCEE_TDP_TRP_CNT",
+	"ROCEE_TDP_MDB_CNT",
+	"ROCEE_TDP_LP_CNT",
+	"ROCEE_TDP_QMM_CNT",
+	"ROCEE_TDP_TWP_CNT0",
+	"ROCEE_TDP_TWP_CNT1",
+	"TDP_V_ECC1B",
+	"TDP_V_ECC2B",
+	"TDP_V_ECC_ERR_INFO",
+	"TDP_V_ALM",
+	"TDP_V_STA",
+	"ROCEE_TSP_OOO_ERR",
+	"TDP_M_STA",
+	"TDP_M_STA1",
+};
+
+static const char *g_tsp_tgp_tmp_reg_name[] = {
+	"ROCEE_TGP_ALM0",
+	"ROCEE_TGP_ALM1",
+	"ROCEE_TGP_STA0",
+	"ROCEE_TGP_STA1",
+	"TGP_INDRECT_RD_CTRL",
+	"TGP_INDRECT_RD_STA",
+	"TGP_INDRECT_RD_DATA",
+	"ROCEE_TMP_ALM0",
+	"ROCEE_TMP_ALM1",
+	"ROCEE_TMP_STA0",
+	"ROCEE_TMP_STA1",
+};
+
+static const struct reg_name_info {
+	enum roce_tsp_sub_cmd_code sub_cmd;
+	const char **reg_name;
+	uint8_t arr_len;
+} g_tsp_reg_name_info_table[] = {
+	{COMMON, g_tsp_common_reg_name, HIKP_ARRAY_SIZE(g_tsp_common_reg_name)},
+	{TDP, g_tsp_tdp_reg_name, HIKP_ARRAY_SIZE(g_tsp_tdp_reg_name)},
+	{TGP_TMP, g_tsp_tgp_tmp_reg_name, HIKP_ARRAY_SIZE(g_tsp_tgp_tmp_reg_name)},
+};
+
 static void hikp_roce_tsp_print(uint32_t total_block_num,
 				const uint32_t *offset, const uint32_t *data)
 {
+	const char **reg_name;
+	uint8_t arr_len;
 	uint32_t i;
 
+	for (i = 0; i < HIKP_ARRAY_SIZE(g_tsp_reg_name_info_table); i++) {
+		if (g_tsp_reg_name_info_table[i].sub_cmd != g_roce_tsp_param_t.sub_cmd_code)
+			continue;
+		arr_len = g_tsp_reg_name_info_table[i].arr_len;
+		reg_name = g_tsp_reg_name_info_table[i].reg_name;
+		break;
+	}
+
+	if (i == HIKP_ARRAY_SIZE(g_tsp_reg_name_info_table)) {
+		printf("can't find reg name table for roce_tsp sub_cmd %u.\n",
+		       g_roce_tsp_param_t.sub_cmd_code);
+		return;
+	}
+
 	printf("**************TSP INFO*************\n");
+	printf("%-40s[addr_offset] : reg_data\n", "reg_name");
 	for (i = 0; i < total_block_num; i++)
-		printf("[0x%08X] : 0x%08X\n", offset[i], data[i]);
+		printf("%-40s[0x%08X] : 0x%08X\n",
+		       i < arr_len ? reg_name[i] : "",
+		       offset[i], data[i]);
 	printf("***********************************\n");
 }
 
-- 
2.45.0.windows.1

